The present invention relates to digital data processing apparatus and more particularly to apparatus for adjusting the phase of data signals arriving at utilization circuitry so as to compensate for uncontrollable phase shifts originating apart from the data utilization circuitry.
As digital data processing systems have become faster and more complex, an increasingly serious problem has been that of synchronizing the various data and clock signals which are utilized throughout the system. As the data and clock rates are pushed ever higher, the delays associated with even short lengths of wire become significant due to the phase shift they introduce, owing to the finite speed of propagation of pulse signals along the wire. To date, most efforts at dealing with these problems have concentrated on keeping circuit paths as short as possible. Even so, in certain high speed systems it has been necessary to tediously adjust wire or cable lengths on an empirical basis so as to assure that the data and clock signals arrive at a given utilization circuit with the proper phase relationship so that data errors will not occur.
Problems of timing are compounded in multiprocessor systems since it becomes extremely difficult to equalize the transit times between all combinations of subsystems, even though various of these subsystems may each be considered a region of substantially synchronous operation. While it is possible to globally distribute a clock signal of precisely controlled frequency, it is difficult to control relative phasing from one region to another. Another source of timing problems originates with the variation of delay with changing temperature through the various input and output buffer circuits which are normally associated with each data line of significant length.
While the need for phase adjustment in accordance with the present invention is necessitated by the use of very high speed data transfer rates and the relatively significant magnitude of the phase shifts introduced by variations in signal path lengths, it will also be understood that changes in such delays typically occur relatively slowly. Such delays are, for example, introduced by the heating up of the transistor junctions which comprise the digital logic gates generating and receiving the data signals. Accordingly, while the initial adjustment needed may not be known and the cause of changes in phase shift may be both unknown and unpredictable, it is not necessary to make adjustments at a relatively high rate since the changes will be relatively gradual once the system is up and operational.
Among the several objects of the present invention may be noted the provision of apparatus for automatically adjusting the phase of data signals arriving at utilization circuitry so as to compensate for uncontrollable phase shifts originating apart from the utilization circuitry; the provision of such apparatus which will operate automatically; the provision of such apparatus which facilitates very high speed operations; the provision of such apparatus which facilitates the cooperative operation of multiple regions of synchronous behavior in a digital data processing system; the provision of such apparatus which is highly reliable and which is of relatively simple and inexpensive construction. Other objects and features are in part apparent and in part be pointed out hereinafter.